Flash memory is a type of EEPROM that allows multiple memory locations/regions to be erased or written/programmed in one programming operation. In a conventional EEPROM, only one memory location/region at a time may be erased or programmed. As such, flash memory devices can be operated at higher effective speeds when systems employing flash memory devices read and write to more than one memory region at the same time. Many types of flash memory and/or EEPROM may “wear out” after a certain number of erase operations, for example, due to wear on the insulating layers covering charge storage means used in storing data.
Flash memory devices are non-volatile devices, which can store information on a silicon chip in a manner that may not require power to maintain the information stored in the silicon chip. In other words, information may be stored in flash memory devices even if power is cut off. In addition, flash memory devices may provide a resistance to physical impact and relatively fast read access times. Accordingly, flash memory devices may be used for storage in battery-powered devices. Flash memory devices may be classified into two groups, NOR flash and NAND flash, based on the type of logic gate used in each storage device.
Flash memory devices may store information in an array of transistors, called “cells”, each of which may store 1-bit of information. Newer flash memory devices (called “multi-level devices”) can store more than 1-bit per cell, by varying the number of electrons stored on the floating gate of a cell.
A NOR-type flash memory device may be similar to a standard MOSFET transistor, except that each cell may have two gates. One gate may be a control gate CG similar to other MOS transistors, while the second gate may be a floating gate FG insulated by an oxide layer. The floating gate may be located between the control gate and the (bulk) substrate. Since the floating gate may be insulated by the oxide layer, electrons on the floating gate may be trapped, and accordingly, information may be stored. When electrons are trapped on the floating gate, an electric field from the control gate may be modified (i.e., at least partially cancelled out), which may modify a threshold voltage Vt of the cell. Thus, when the cell is “read” by applying a specific voltage to the control gate, electrical current may either flow or not flow depending on the threshold voltage of the cell, which may be controlled by the electric charge on the floating gate. The presence or absence of current may be sensed and interpreted as “1” or “0”, to reproduce the stored data. In a multi-level cell device, which may store more than 1-bit per cell, the amount of current, rather than the presence or absence of current, may be sensed to determine the number of electrons stored on the floating gate.
A NOR-type flash cell may be programmed (set to a specific data value) by applying a program voltage to the control gate. Under these bias conditions, a relatively large amount of current may flow from a drain to a source in a process called “hot-electron injection”. In order to erase the NOR-type flash cell, a relatively large voltage differential is applied between the control gate and the substrate (or bulk), which may remove electrons from the floating gate via Fowler-Nordheim tunneling. NOR-type flash memory devices may be divided into erase segments, which may be called “blocks” or “sectors”. All memory cells in a sector may be erased at the same time. NOR programming, however, may be performed one byte or word unit at a time.
Erase operations in a NOR-type flash memory device may include a pre-program operation, a main erase operation, and a post-program operation. The pre-program operation may be performed using bias conditions similar to a program operation, which may prevent memory cells from being over-erased into depletion in a subsequent main erase operation. All memory cells in a sector to be erased may be pre-programmed. Next, a main erase operation may be performed such that all memory cells in the sector may have an on-state. Finally, a post-program operation may be performed to adjust the threshold voltage Vt of the memory cells that are erased in the main erase interval to approximately the same level. Except for the bias conditions, the post-program operation may be performed in a manner similar to that of the pre-program operation. In other words, memory cells connected to each of word lines (or rows) may be post-programmed one byte or word unit at a time.
However, because NOR post-programming operations may be performed one byte or word unit at a time, NOR-type flash memory devices which employ the above-described erase operations may require a relatively long interval of time to perform the pre-program and post-program operations of the erasing process.